Regviz

Silicon Labs /MGM240PB32VNN /EMU_NS /PD1PARETCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PD1PARETCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32MG24A120F1536GM48/EMU_S/PD1PARETCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PD1PARETDIS

Description

No Description

Fields

PD1PARETDIS

Disable PD1 Partial Retention

1 (PERIPHNORETAIN): Retain associated registers when in EM2/3

2 (RADIONORETAIN): Bit[1]. When set, do not retain RADIO associated registers when in EM2/3

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data